A semiconductor image sensor is characterized in each cell has a photo detecting section sensitive to light and having a light amplifying function and a switch for matrix selecting use is formed by a single transistor, that is, each cell is formed by a static induction transistor featuring high sensitivity and high-speed operation.
Conventional semiconductor image sensors have each cell comprised of a diode for photodetecting use and a MOS transistor for switching use and performs photodetection by the diode, and hence has the defect of low sensitivity.
Further, they have such a drawback that since the MOS transistor is employed for switching, switching noise is larger than a light signal and a circuit for removing noise is complex. For these reasons, the use of the cell comprised of the photodetecting diode and the MOS transistor imposes limitations on the integration density of the image sensor in terms of sensitivity.
The present inventor has already disclosed in Japanese Pat. Appln. No. 204656/81 a one cell-one transistor type semiconductor device which employs the same static induction transistor of high photosensitivity both for photodetection and for switching. But the disclosed SIT image sensor lacked concreteness in a method of operation and a method of signal separation between cells.
The present invention is to provide a novel semiconductor image sensor by the introduction of a novel cell structure for improving the method of signal separation between cells and raising the integration density in the disclosed semiconductor image sensor.
Conventional semiconductor image sensors are shown FIGS. 1A and B. In FIGS. 1A and B, reference numeral 1 indicates a silicon n.sup.+ substrate, 2 a high resistance n.sup.- layer of an intrinsic semiconductor region, 3 a high impurity density n.sup.+ region which will ultimately serve as a source or drain, 4 a high impurity density p.sup.+ region which will ultimately serve as a first gate, and 5 a high impurity density p.sup.+ region which will ultimately serve as a second gate. Reference numeral 8 designates a source or drain electrode, 10 a drain or source electrode, 6 a film of an insulating material such as an SiO.sub.2, Si.sub.3 N.sub.4 or the like, 7 a first gate electrode, and 9 a surface protective film such as an SiO.sub.2 film or the like. Reference numeral 11 identifies a switching transistor, and 12 a circuit which generates a pulse voltage .phi..sub.s for video line selection which controls the switching transistor 11. Reference numeral 13 denotes an address circuit which generates a pulse voltage .phi..sub.G which is supplied to the first gate for readout, 14 a load resistor of the switching transistor, 15 a video voltage source for a photoconductive cell section, and 16 wiring (a video line) to the switching transistor 11 and the load resistor 14. Reference numeral 18 represents an optical input.
The high impurity density p.sup.+ region 5 of the second gate is held in an electrically floating state, or retained at a fixed voltage by a predetermined bias circuit.
In FIG. 1A, the surface n.sup.+ region 3 and its electrode 8 are grounded, whereas in FIG. 1B the n.sup.+ substrate region 1 is grounded.
FIG. 1C shows a readout circuit of one cell as in FIG. 1A. In FIG. 1A, since the high impurity density n.sup.+ region 3 which will ultimately form the source is grounded, the source of the SIT is grounded also in FIG. 1C. In the readout circuit of one cell as in FIG. 1B, though not shown, the indication of the SIT is the reverse from that in the above case, since the n.sup.+ substrate region which serves as an n.sup.+ drain is grounded. Accordingly, the operation of the SIT is the reverse from that of the SIT in the above case.
In FIG. 1C, when the pulse voltage .phi..sub.s is applied to the base or gate of the transistor 11 to cause it to conduct and the voltage of the video voltage source 15 is provided to a phototransistor 19 shown in the sectional view of FIG. 1A, an optical signal is written by the optical input 18. At this time, the voltage .phi..sub.G is not being supplied. When the voltage .phi..sub.G is applied to conduct the phototransistor 19, a drain current is produced corresponding to the optical input 18, obtaining an optical output signal from an output terminal 17. The optical output at the output terminal 17 varies in accordance with the intensity of the optical input 18; this provides the characteristic of a large dynamic range, leading to such a feature that the light amplification factor is larger than those obtainable with conventional bipolar transistors.
FIG. 1D shows an example of the optical dynamic characteristic of one cell of the image sensor of the SIT shown in FIG. 1B. The device measures about 50.times.55.mu. and has a gate storage capacitance of approximately 5 pF and a light integration time of 25 msec.
In the phototransistors shown in section in FIGS. 1A and B, the distance W.sub.1 between the high impurity density p.sup.+ region 4 serving as the first gate and the high impurity density n.sup.+ region 3 serving as the source and the distance W.sub.2 between the p.sup.+ region 5 serving as the second gate and the n.sup.+ region 3 of the source are substantially equal, and optically excited carriers are stored in the first and second gates with substantially the same probability, so that voltage variations of the first and second gates make substantially the same contribution to a source-to-drain signal current.
The reason for this is that since a diffusion potential Vb.sub.1 between the p.sup.+ region 4 of the first gate and the n.sup.+ region 3 of the source and a diffusion potential Vb.sub.2 between the p.sup.+ region 5 of the second gate and the n.sup.+ region 3 of the source are nearly equal, the potential barriers of the first gate 4 and the second gate 5 with respect to the source are reduced substantially the same extent when the optical signal 18 is applied. Therefore, even if the second gate is floating, a photoelectric conversion current flows in the channel region between the second gate 5 and the n.sup.+ region 3 of the source to substantially the same extent as in the channel region between the first gate 4 and the n.sup.+ region 3 of the source owing to the lowered potential barrier, making it impossible to fix the potential of the second gate 5 with respect to the channel.